SR Flip Flop

SR Flip Flop
Introduction
SR Flip Flop Using NAND Gates
SR Flip Flop Using NOR Gates
SR Flip Flop as Data Storage Device
SR Flip Flop as Switch Debounce circuit

INTRODUCTION

The SR Flip Flop is one of the fundamental parts of the sequential circuit. SR is a digital circuit and binary data of a single bit is being stored by it. RS Flip Flop has two stable states in which it can store data i.e. either binary zero or binary one. The Flip Flop has remained in the state until we changed the state i.e. if the RS is set to binary one then it will remain in that state until we changed the state or the power is off. It implies that the flip flop memorize the state in which it was earlier set and remember the date that given to it.

SR Flip Flop is the most vital as well as broadly used Flip Flop. It is further more acknowledged as SET-RESET Flip Flop. Below the symbolic representation of the SR Flip Flop is shown.

SR flip flop

Working

When clock pulse is high i.e. logic 1 the data will transfer from S and R inputs to the output. Suppose, if SET input is at high level (1) , RESET input is at low level (0) and clock pulse is also high logic level(1) , then the S R flip flop is in SET state , because the clock pulse allows the SET input to the output. So the information from S and R inputs reaches the output.

truth table

The S R Flip Flop can be designed by using logic gates like NOR gates and NAND gates. Example with NAND gate is shown below.

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S-R FLIP-FLOP USING NAND GATE

As we said earlier, an S R flip flop can be designed by cross coupling of two NAND gates, it is called “Active LOW input S-R flip flop”. It is shown in below figure.

SR using nand gate

The two inputs of S R flip flop are connected as a single input to each of two NAND gates and the output of the NAND gates are connected back as feedback inputs.

Working

Case 1:

When both the SET and RESET inputs are high, then the output remains in previous state.

Case 2:

When SET input is HIGH and RESET input is LOW, then the flip flop will be in RESET state. Because the low input of R drives the second NAND gate to its output as 1. So both the inputs of the first NAND gate are 1 and 1. This will cause the output of the flip flop to settle in RESET state.

Case 3:

When SET input is LOW and RESET input is HIGH, then the flip flop will be in SET state. Because the low input of the S input drives the first NAND gate to its output as 1. So both the inputs of the second NAND gate are 1 and 1. This will cause the output of the flip flop to settle in SET state.

Case 4:

When both the SET and RESET inputs are low, then the flip flop will be in undefined state. Because the low inputs of S and R, violates the rule of flip flop , the outputs should compliment to each other. So the flip flop is in undefined state (or forbidden state).

The table below summarizes above explained working of SR Flip Flop designed with the help of a NAND gate.

SR using nand gate truth table

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S R FLIP-FLOP USING NOR GATE

When S R flip flop is designed by cross coupling of two NOR gates, it is called “Active HIGH input S-R flip flop”. It is shown in below figure.

SR using nor gate

The inputs of S R flip flop are connected as an single input to each of two NOR gates and the output of the NOR gates are connected back as feedback inputs.

Working

Case 1:

When both the SET and RESET inputs are low, then the output remains in previous state.

Case 2:

When SET input is low and RESET input is high, then the flip flop will be in RESET state. Because the high input of the R input drives the first NOR gate to its output as 0. So both the inputs of the first NOR gate are 0 and 0. This will cause the output of the flip flop to settle in RESET state.

Case 3:

When SET input is high and RESET input is low, then the flip flop will be in SET state. Because the low input of the S input drives the second NOR gate to its output as 1. So both the inputs of the first NOR gate are 1 and 1. This will cause the output of the flip flop to settle in SET state.

Case 4:

When both the SET and RESET inputs are high, then the flip flop will be undefined state. Because the high inputs of S and R, violates the rule of flip flop that the outputs should compliment to each other. So the flip flop is in undefined state (or forbidden state).

The table below summarizes above explained working of SR Flip Flop designed with the help of a NOR gate.

sr using nor gate truth table

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APPLICATIONS

S R flip flops are very simple but mostly used in different types of digital circuits .Their applications are seen in many fields in digital electronics. They are

  • Data Storage
  • A switch de-bouncer

 Data storage device

In digital circuits, Flip flops can store one bit of data, at a time. To store more than one bit of information, flip flop can be connected in series and parallel. This series and parallel arrangement of flip flops is called “Registers”. A register is a data storage device for storing number of bits. In a register, each flip flop will store one bit of information. So a 4 bit register consists of 4 S R flip flops, each able to store one bit of information, at the same time.

sr as a data storage element

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Switch de bounce circuit

The S R flip flops are used to eliminate mechanical bounce in digital circuits.

Mechanical Bounce

“Mechanical bounce” means when we press a button in keyboard or push button, then it will operate at low and high voltages which can be interpreted by digital circuit. Mechanical bounce occurs , when the surface of any mechanically operated switches are made in contact.

switch debounce

This can result in variation of pulse signals. These series of unwanted pulses will result in the digital system to work incorrectly.

For example, in this bouncing period of the signal, the fluctuations in the output voltage are very high and therefore the register counts several inputs instead of single input. To eliminate this kind of  behaviour of digital circuits, we use Set-Reset flip flops or bi-stable flip flops i.e. S R flip flop.

HOW DOES S R FLIP-FLOP ELIMINATES THE MECHANICAL BOUNCE

Based on the present state output, if the set or reset buttons are depressed then the output will change in a manner that it counts more than one signal input i.e. the circuit may receive some unwanted pulse signals and thus because of the mechanical bouncing action of machines, there is no change in outputs at Q.

image 9

When the button is pressed, the contact will affect the flip flop input and there will be change in the present state and no further affects on the circuit/machine for any other mechanical switch bounces. If there is any additional input from the switch , there will be no change and SR flip flop will reset after some small period of time.

So the same switch will come to use only after an S R flip flop executes a state change i.e. only after receiving the single clock pulse signal.

Commonly used ICs for eliminating the mechanical switch bounce are MAX6816 – single input,

MAX6817 – dual input, MAX6818 – octal input switch de-bouncer ICs. These ICs contains the necessary configuration with the S-R flip flops.

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