T flip – flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state in SR flip – flop, we should provide only one input to the flip – flop called Trigger input or Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the next state output to complement of the present state output’.
We can design the T flip – flop by making simple modifications to the JK flip – flop. The T flip – flop is a single input device and hence by connecting J and K inputs together and giving them with single input called T we can convert a JK flip – flop into T flip – flop. So a T flip – flop is sometimes called as single input JK flip – flop.
T Flip – flop Circuit
We can construct a T flip – flop by any of the following methods.
Connecting the output feedback to the input, in SR flip – flop.
Connecting the XOR of T input and Q PREVIOUS output to the Data input, in D flip – flop.
Hard – wiring the J and K inputs together and connecting it to T input, in JK flip – flop.
We can construct a T flip – flop by connecting AND gates as input to the NOR gate SR latch. And these AND gate inputs are fed back with the present state output Q and its complement Q’ to each AND gate. A toggle input (T) is connected in common to both the AND gates as an input. The AND gates are also connected with common Clock (CLK) signal. In the T flip – flop, a pulse train of narrow triggers are provided as input (T) which will cause the change in output state of flip – flop. So these flip – flops are also called Toggle flip – flops. The circuit diagram of a T flip – flop constructed from SR latch is shown below
Similarly, a T flip – flop can be constructed by modifying D flip – flop. In D flip – flop, the output QPREV is XORed with the T input and given at the D input. The circuit of a T flip – flop constructed from a D flip – flop is shown below.
The simplest of the constructions of a D flip – flop is with JK flip – flop. The J input and K input of the JK flip – flop are connected together and provided with the T input. The logic circuit of a T flip – flop constructed from a JK flip – flop is shown below.
T flip – flop is an edge triggered device i.e. the low to high or high to low transitions on a clock signal of narrow triggers that is provided as input will cause the change in output state of flip – flop.
Truth Table of T flip – flop
The truth table of a T flip – flop is shown below.
As mentioned earlier, T flip – flop is an edge triggered device. For example, consider a T flip – flop made of NAND SR latch as shown below.
If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in disable condition. This allows the trigger to pass the S inputs to make the flip – flop in SET state i.e. Q = 1.
If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in enable condition. This allows the trigger to pass the R inputs to make the flip – flop in RESET state i.e. Q =0.
In simple terms, the operation of the T flip – flop is
When the T input is low, then the next sate of the T flip flop is same as the present state.
- T = 0 and present state = 0 then the next state = 0
- T = 1 and present state = 1 then the next state = 1
When the T input is high and during the positive transition of the clock signal, the next state of the T flip – flop is the inverse of present state.
- T = 1 and present state = 0 then the next state = 1
- T = 1 and present state = 1 then the next state = 0
As each incoming trigger alternately changes the set and reset inputs, the flip – flop toggles. So to complete one full cycle of output wave form it need two triggers. This means that the T flip flop produces the output at exactly half of the frequency of input frequency. So a T flip – flops will act as “Frequency Divider Circuit”.
The main disadvantage of T flip – flop is that the state of the flip – flop at an applied trigger pulse is known only when the previous state is known.
Generally, T flip flops are not available as ICs. So they can be constructed by using JK flip – flop and SR flip – flop and D flip – flop. The symbol of T flip – flop made from JK flip – flop is shown below.
- Frequency Division Circuits.
- 2 – Bit Parallel Load Registers.
Frequency Division Circuit
A T flip – flop can be used as a Frequency Divider Circuit by feeding back the complementary output Q’ to the T input.
The logic symbol of a frequency divider using T flip – flop is shown below.
We use registers and shift registers to store the data. But size is always a primary concern for memory elements such as registers. So we use 2 – bit parallel load registers instead 4 – bit registers.
There are two operations to be considered when designing a parallel load register: hold the data and parallel load the data.
To hold the output of T flip – flop, the input T should be 0.
Parallel load is the difficult part. Parallel load means to get the value X at the output of the flip – flop. In order to do that, we XOR the X input and present state output and give it to 2 to 1 MUX. The other input to the MUX is a constant 0 (logic low). The output of the MUX is connected to the input of the T flip – flop. Since it is a 2 – bit register, two such combinations are needed. The circuit of a 2 – bit parallel load register is shown below.