The action or operation of a demultiplexer is opposite to that of the multiplexer. As inverse to the MUX , demux is a one-to-many circuit. With the use of a demultiplexer , the binary data can be bypassed to one of its many output data lines.
Demultiplexers are mainly used in Boolean function generators and decoder circuits. Different input/output configuration demultiplexers are available in the form of single integrated circuits (ICs).
Also, the facility of cascading two or more IC circuits helps to generate multiple output demultiplexers. Let us get a brief idea of demultiplexers and its types.
What is Demultiplexer?
The process of getting information from one input and transmitting the same over one of many outputs is called demultiplexing. A demultiplexer is a combinational logic circuit that receives the information on a single input and transmits the same information over one of 2n possible output lines.
The bit combinations of the select lines control the selection of specific output line to be connected to the input at given instant. The below figure illustrates the basic idea of demultiplexer , in which the switching of the input to any one of the four outputs is possible at a given instant.
Demultiplexers are also called as data distributors, since they transmit the same data which is received at the input to different destinations.
Thus, a demultiplexer is a 1-to-N device where as the multiplexer is an N-to-1 device. The figure below shows the block diagram of a demultiplexer or simply a DEMUX.
It consists of 1 input line, n output lines and m select lines. In this, m selection lines are required to produce 2m possible output lines (consider 2m = n). For example, a 1-to-4 demultiplexer requires 2 (22) select lines to control the 4 output lines.
There are several types of demultiplexers based on the output configurations such as 1:4, 1:8 and 1:16.
These are available in different IC packages and some of the most commonly used demultiplexer ICs includes 74139 (dual 1:4 DEMUX), 73136 (1:8 DEMUX), 74154 (1:16 DEMUX), 74159 (1:16 DEMUX open collector type), etc.
A 1-to-2 demultiplexer consists of one input line, two output lines and one select line. The signal on the select line helps to switch the input to one of the two outputs. The figure below shows the block diagram of a 1-to-2 demultiplexer with additional enable input.
In the figure, there are only two possible ways to connect the input to output lines, thus only one select signal is enough to do the demultiplexing operation. When the select input is low, then the input will be passed to Y0 and if the select input is high then the input will be passed to Y1.
The truth table of a 1-to-2 demultiplexer is shown below in which the input is routed to Y0 and Y1 depends on the value of select input S. In the table output Y1 is active when the combination of select line and input line are active high, i.e., S F = 11.
Therefore, the output Y1 = SF and similarly the output Y0 is equal to S ̅ F.
From the above truth table, the logic diagram of this demultiplexer can be designed by using two AND gates and one NOT gate as shown in below figure. When the select lines S=0, AND gate A1 is enabled while A2 is disabled.
Then, the data from the input flows to the output line Y1. Similarly, when S=1, AND gate A2 is enabled and AND gate A1 is disabled, thus data is passed to the Y0 output.
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and four outputs (Y0 to Y3). The input data goes to any one of the four outputs at a given time for a particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two select lines and 4 output lines. The block diagram of 1:4 DEMUX is shown below.
The truth table of this type of demultiplexer is given below. From the truth table it is clear that, when S1=0 and S0= 0, the data input is connected to output Y0 and when S1= 0 and s0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of select lines.
From the table, the output logic can be expressed as min terms and are given below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.
From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented by using four 3-input AND gates and two NOT gates as shown in figure below. The two selection lines enable the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the selected gate to the associated output.
This type of demultiplexer is available in IC form and a typical IC 74139 is most commonly used dual 1-to-4 demultiplexer. It has two independent demultiplexers and each DEMUX accepts two binary inputs as select lines and four mutually exclusive active-low outputs.
Both demultiplexers share a common set of selection lines so they are selected in parallel. Also, each demultiplexer consists of enable pin or data input, for one demultiplexer it is active high data input and for other it is active low data input.
The below figure shows the block diagram of a 1-to-8 demultiplexer that consists of single input D, three select inputs S2, S1 and S0 and eight outputs from Y0 to Y7.
It is also called as 3-to-8 demultiplexer due to three select input lines. It distributes one input line to one of 8 output lines depending on the combination of select inputs.
The truth table for this type of demultiplexer is shown below. The input D is connected with one of the eight outputs from Y0 to Y7 based on the select lines S2, S1 and S0.
For example, if S2S1S0=000, then the input D is connected to the output Y0 and so on.
From this truth table, the Boolean expressions for all the outputs can be written as follows.
From these obtained equations, the logic diagram of this demultiplexer can be implemented by using eight AND gates and three NOT gates as shown in below figure. The different combinations of the select lines , select one AND gate at given time , such that data input will appear at a particular output.
A typical IC74237 is a 1-to-8 demultiplexer that consists of latches at three select inputs. The pin out of this IC is given below.
The pins A0 to A2 are data inputs, Y0 to Y7 are demultiplexer outputs, E1&E2 are active-low data enable and active-high data enable pins respectively, LE is the latch enable input ,Vcc and GND terminals are positive supply voltage and ground terminals.
With a 3-bit storage latch, this IC combines the 3-to-8 decoder function.
1-to-8 DEMUX using Two 1-to- 4 Demultiplexers
When the application requires a large demultiplexer with more number of output pins, then we cannot implement by a single integrated circuit. In case if more than 16 output pins are needed, then two or more demultiplexer ICs are cascaded to fulfill the requirement.
For example, if the application needs 32 output lines from a DEMUX, then we cascade two 1:16 demultiplexers or three 1:8 demultiplexers. Therefore, by cascading the two or more demultiplexers, a large demultiplexer can be implemented.
Consider the case that a 1-to-8 demultiplexer can be implemented by using two 1-to-4 demultiplexers with a proper cascading.
In the above figure, the highest significant bit A of the selection inputs are connected to the enable inputs such that it is complemented before connecting to one DEMUX and to the other it is directly connected.
By this configuration, when A is set to zero, one of the output lines from Y0 to Y3 is selected based on the combination of select lines B and C. Similarly, when A is set to one, based on the select lines one of the output lines from Y4 to Y7 will be selected.
Implementation of Full Subtractor Using 1-to-8 DEMUX
As similar to the multiplexers, demultiplexers are also used for Boolean function implementation as well as combinational circuit design. We can design the demultiplexer to produce any truth table output by correspondingly controlling the select lines.
Consider the case for implementing a demultiplexer circuit in order to produce the full subtractor output. The truth table below shows the output of a full subtractor.
From the above table, the full subtractor output D can be written as
D = f (A, B, C)
= ∑m (1, 2, 4, 7)
And the borrow output can be expressed as
Bout = F (A, B, C) = ∑m (1, 2, 3, 7)
From these Boolean functions, a demultiplexer for producing full subtractor output can be built by properly configuring the 1-to-8 DEMUX such that with input D=1 it gives the minterms at the output.
And by logically ORing these minterms, the outputs of difference and borrow can be obtained as shown in figure.
Applications of Demultiplexer
Since the demultiplexers are used to select or enable the one signal out of many, these are extensively used in microprocessor or computer control systems such as
- Selecting different IO devices for data transfer
- Choosing different banks of memory
- Depends on the address, enabling different rows of memory chips
- Enabling different functional units.
Other than these, demultiplexers can be found in a wide variety of application such as
- Synchronous data transmission systems
- Boolean function implementation (as we discussed full subtractor function above)
- Data acquisition systems
- Combinational circuit design
- Automatic test equipment systems
- Security monitoring systems (for selecting a particular surveillance camera at a time), etc.