Adders are digital circuits that carry out addition of numbers. Adders are a key component of Arithmetic Logic unit. Adders can be constructed for most of the numerical representations like Binary Coded Decimal (BDC), Excess – 3, Gray code, Binary etc. out of these, binary addition is the most frequently performed task by most common adders. Apart from addition, adders are also used in certain digital applications like table index calculation, address decoding etc.
Binary addition is similar to that of decimal addition. Some basic binary additions are shown below.
The adder that performs simple binary addition must have two inputs (augend and addend) and two outputs (sum and carry). The device which performs above task is called a Half Adder.
Half adder is a combinational circuit that performs simple addition of two binary numbers. The block diagram of a half adder is shown below.
Half Adder Truth Table
If we assume A and B as the two bits whose addition is to be performed, a truth table for half adder with A, B as inputs and Sum, Carry as outputs can be tabulated as follows.
The sum output of the binary addition carried out above is similar to that of an Ex-OR operation while the carry output is similar to that of an AND operation. The same can be verified with help of Karnaugh Map.
The truth table and K Map simplification for Sum output is shown below.
Sum = A B ̅ + A ̅ B.
Hence the logic diagram for sum is shown below.
The truth table and K Map simplification for carry is shown below.
Carry = AB
The logic diagram for carry is shown below.
If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR of A and B and logic function to calculate carry C is AND of A and B. Combining these two, the logical circuit to implement the combinational circuit of Half Adder is shown below.
As we know that NAND and NOR are called universal gates as any logic system can be implemented using these two, the half adder circuit can also be implemented using them. We know that a half adder circuit has one Ex – OR gate and one AND gate.
Half Adder using NAND Gates
Five NAND gates are required in order to design a half adder. The circuit to realize half adder using NAND gates is shown below.
Also get an idea about How to Build OR, AND, NOT Gates using NAND Gate
Half Adder using NOR Gates
Five NOR gates are required in order to design a half adder. The circuit to realize half adder using NOR gates is shown below
Limitations of Half Adder
The reason these simple binary adders are called Half Adders is that there is no scope for them to add the carry bit from previous bit. This is a major limitation of half adders when used as binary adders especially in real time scenarios which involves addition of multiple bits. To overcome this limitation, full adders are developed.
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Full adder is a digital circuit used to calculate the sum of three binary bits which is the main difference between this and half adder. Full adders are complex and difficult to implement when compared to half adders. Two of the three bits are same as before which are A, the augend bit and B, the addend bit. The additional third bit is carry bit from the previous stage and is called Carry – in generally represented by CIN. It calculates the sum of three bits along with the carry. The output carry is called Carry – out and is represented by COUT.
The block diagram of a full adder with A, B and CIN as inputs and S, CoUT as outputs is shown below
Full Adder Truth Table
The truth table for full adder is shown below.
Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be derived using K – Map.
For Sum S
The simplified equation for sum is S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
For Carry – out COUT
The simplified equation for COUT is COUT = AB + ACIN + BCIN
In order to implement a combinational circuit for Full Adder, it is clear from the equations derived above, that we need 4 three input AND gates and 1 four input OR gate for Sum and 3 two input AND gates and I three input OR gate for Carry – out.
The logic circuit for full adder is shown below.
Implementation of Full Adder using Half Adders
A full adder can be formed by logically connecting two half adders. The block diagram that shows the implementation of a full adder using two half adders is shown below.
S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
Cout = AB + ACin + BCin
We can rewrite the equation for sum as follows.
S = A ̅ B ̅ Cin + A ̅ BC ̅ in + ABCin
= Cin (A ̅ B ̅ + AB) + C ̅ in (A ̅ B + A B ̅ )
Therefore S = CIN XOR (A XOR B)
= Cin (A X-NOR B) + C ̅ in (A X-OR B)
= Cin XOR (A XOR B)
Cout is simplified as
COUT = A B + A CIN + B CIN.
COUT = AB + A CIN + B CIN (A + ̅A)
= ABCIN + AB + ACIN + ̅A B CIN
= AB (1 +CIN) + ACIN + ̅A B CIN
= A B + ACIN + ̅A B CIN
= AB + ACIN (B + ̅B ) + ¬ ̅A B CIN
= ABCIN + AB + A ̅B CIN + ̅A B CIN
= AB (CIN + 1) + A ̅B CIN + ̅A B CIN
= AB + A ̅B CIN + ̅A B CIN
= AB + CIN ( ̅AB + A ̅B )
Therefore COUT = AB + CIN (A EX – OR B)
Based on the above two equations, the full adder circuit can be implemented using two half adders and an OR gate. The implementation of full adder using two half adders is show below.
Full Adder using NAND Gates
As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement any logic design. The circuit of full adder using only NAND gates is shown below.
Full adder is a simple 1 – bit adder. If we want to perform n – bit addition, then n number of 1 – bit full adders should be used in the form of a cascade connection.