Ex or gate is the exclusive OR gate. This is not frequently used as inclusive OR gate which is nothing but OR gate. But XOR gate has its own significance. This article explains about XOR gate (Exclusive OR gate) .

### XOR Gate

#### XOR Symbol

There are multiple standards for defining an electronic component. Generally we follow IEEE (Institute of Electrical and Electronics Engineers) and IEC (International Electro-technical Commission) standards. The XOR logic symbol in IEEE and IEC standards is shown below.

As discussed earlier, the Boolean expression for XOR gate cannot determined directly like AND, OR gates. As it is a Hybrid gate, the Boolean expression of output of XOR gate is given by combining Multiplication, Addition and revering of inputs.

If A, B are the inputs of XOR gate, its output is given as A.B ̅ +( A) ̅.B. It can also be said as (A + B). (A ̅ + B ̅). By applying Demorgan’s law, the output of Boolean expression is also written as (A + B). ((A.B) ̅).

The XOR output is represented as A B.

#### XOR Truth Table

The truth table of XOR gate is shown in the below table. From this , it is clear that XOR gate produces a low logic that is logic ‘0’ , at its output , when both the inputs are same .When the two inputs are different it produces a logic high value i.e logic ‘1’ at its output.

#### XOR Gate equivalent circuit

The EX-OR gate is defined as, the hybrid logic gate with 2 or more inputs to perform the exclusive Disjunction operation. The XOR circuit with 2 inputs is designed by using AND, OR and NOT gates is shown above.

The output of 2 input XOR gate is HIGH only when one of its inputs are high. If both the inputs are same, then the output is LOW.

### XOR Gate using Basic logic gates

If a specific gate is not available directly, we will design that gate by using multiple gates. An EX-OR gate can be designed by using basic logic gates like NAND gate and NOR gate.

#### With NOR Gates

#### With NAND Gates

#### Using AND, OR and NAND Gates

### Pulsed Operation

The pulsed operation of 2 input XOR gate is shown below.

### Ex-OR Function Realization using NAND gates

Q= A B = A’B + AB’ = A’B + AB’ + AA’ + BB’ = (A + B) (A’ + B’)

Now we need to implement this circuit using NAND gates

Q= (A + B) (AB)’ = A . (AB)’ + B . (AB)’

Taking compliment

Q’= ( A. (AB)’ + B. (AB)’ )’ = (A. (AB)’)’. (B. (AB)’)

Taking compliment again

Q= ( (A. (AB)’)’. (B. (AB)’) )’

Now we can implement XOR gate using NAND gates

### Ex-OR Function Realization using NOR gates

Q= A B = A’B + AB’ = A’B + AB’ + AA’ + BB’ = (A + B) (A’ + B’)

Q’= A’ (A+B) + B’(A+B)

By applying compliment

Q= (A’ (A + B) + B’ (A + B))’ = (A’(A + B) )’ . (B’ (A + B))’ =(A + (A + B)’). (B + (A + B)’)

By applying compliment again

Q’= ( (A + (A + B)’). (B + (A + B)’) )’ = (A + (A + B)’)’ + (B + (A + B)’)’

Applying compliment again

Q= [ (A + (A + B)’)’ + (B + (A + B)’)’ ]’

Now we can implement the XOR gate using NOR gates.

### 3-input Ex-OR Gate

We can have XOR gate with more than 2 inputs, in some cases. More than 2 input XOR function is called as “Odd function” or “Modulo-2 sum”. The Boolean function for the 3- input XOR gate is

Q = A B C = ABC + A’B’C + A’BC’ + AB’C’.

The truth table and logic symbol for 3-input XOR gate is given below.

#### 3-Input Ex-OR gate logic symbol

#### Truth table of 3 input xor gate

For XOR gates, we can have the HIGH input when odd numbers of inputs are at HIGH level. So the 3-input OR gate is called as “Odd functioned OR gate”.

### Commonly available TTL and CMOS logic Ex-OR gate IC’s

The commonly available XOR ICs list is given below

#### Most used TTL and CMOS logic XOR ICs are

TTL Logic Ex-OR Gates CMOS Logic Ex-OR Gates

74LS86 Quad 2-input CD4030 Quad 2-input

#### 7486 Quad 2-input Exclusive-OR Gate IC

IC 7486 is used as quad 2-input XOR gate. The IC diagram is shown below.

### Ex-OR gate applications

X-OR logic gate is used in many applications. Some of them are explained below.

#### Uses in addition

We can design single bit adder, which will add two bits and produce a single bit output. The single bit Adder designed by using XOR gate is shown below.

For example, if we add two bits 1 and 1 in binary addition, we get the answer 10 and in decimal addition method we get 2. The main principle of half adders is that the trailing sum is achieved by the output of XOR gate and the carry bit is calculated by AND gate.

We can cascade many single bit adder circuits to form n-bit adder circuit, to calculate the sum of longer binary numbers.

#### Pseudo-random number generation

Linear shift registers are also called as Pseudo Random Number Generators (PNRs). In order to generate the random numbers, we arrange the XOR logic gate in a specific order by forming a linear feedback shift register.

#### Correlation and sequence detection

XOR gate is capable of producing a low level input i.e. 0 when all of its inputs are high or low. When we are searching a particular bit sequence in a long data sequence, we use XOR gates to find the required data bit sequence. The accuracy of finding the required string of data bits in the target sequence is determined by calculating the number of 0’s obtained. In many communication devices such as decoders and CDMA receivers, we use co-relaters, which are used to extract the parity of a specific Pseudo Random Number sequence in a group of PRN sequence.

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