VLSI stands for Very Large Scale Integration. Generally there are mainly 2 types of VLSI projects – 1. Projects in VLSI based System Design, 2. VLSI Design Projects. You might be confused to understand the difference between these 2 types of projects. Let me now explain to you.

Projects in VLSI based system design are the projects which involve the design of various types of digital systems that can be implemented on a PLD device like a FPGA or a CPLD.

The projects which deal with the semiconductor design are called as Projects in VLSI design. These are very difficult and expensive to implement in real time.

Image Resource: http://en.wikipedia.org/wiki/VLSI_TechnologyWe have already seen the following engineering project ideas:

So, here we are publishing a list of various VLSI projects which are very useful for final year engineering students. These VLSI projects are interesting and helpful in our real life also. You may just go through this list of projects and get good knowledge on VLSI projects.

**VLSI Projects List:**

1 | 3D Lifting based Discrete Wavelet Transform: The main aim of this project is to aid with image coding in order to produce high accurate images without losing any information. To achieve the task, this approach implements a lifting filter based 3D discrete wavelet transform VLSI architecture. |

2 | Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier: The idea of this project is to implement a modified booth encoder using 4 bit SFQ multiplier which gives better performance as compared to the conventional booth encoder. This can be used for critical delay applications. |

3 | An Area-Efficient Universal Cryptography Processor for Smart Cards: This project implements both private and public key supported three cryptography algorithms for smart card applications to provide highly secured user authentication and data communication. |

4 | A High-Speed/Low-Power Multiplier using Spurious Power Suppression Technique: This project is intended to filter out the useless spurious signals of arithmetic units in order to avoid useless transmission of data where this data does not affect the final computing results. In this, SPST technique is applied on multipliers so that high speed and low power data transmission is achieved. |

5 | A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture: The objective of this project is to implement a two-stage hardware architecture based on the features of Parallel dictionary LZW algorithm (PDLZW) and Adaptive Huffman algorithm for both lossless data compression and lossless decompression applications. |

6 | Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks: This project reduces the overall energy consumption during transmission of data of wireless sensor networks by decomposing LUT-Log-BCJR algorithm into fundamental Add Compare Select (ACS) operations. |

7 | An Efficient VLSI Architecture for Removal of Impulse Noise in Image : This project aims to enhance the visual quality of images and to avoid chances of being corrupted by impulse noise by implementing an efficient VLSI architecture using edge preserving filter. |

8 | A Processor-In-Memory Architecture for Multimedia Compression: This project presents the implementation of a low complexity processor-in memory architecture that supports for multimedia applications like video and image compression by applying very large instruction word and single-instruction and multiple data concepts. |

9 | A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems: This project enhances the performance of wireless Orthogonal Frequency Division Multiplexing system by reducing the total base band power using phase tunable clock generator and dynamic sample-timing controller. |

10 | Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog: This project aims to design high speed and low power Multiplier and Accumulator (MAC) by adopting the Spurious Power Suppression Technique on a modified booth encoder. By this design overall switching power dissipation is avoided. |

11 | Design and VLSI Implementation of Anti-collision Enabled Robot Processor Using RFID Technology: This project implements anti-collision based robot processor for avoiding physical collision of robots in multi-robot environment. This algorithm is implemented with the help of RFID technology by using VHDL. |

12 | Adiabatic Technique for Power Efficient Logic Circuit Design: This project illustrates the efficient logic circuit design using adiabatic technique as compared with conventional CMOS design using NAND and NOR circuits. With the use of adiabatic technique, the power dissipation in the network is minimized and also it can recycle the energy stored in the load capacitor. |

13 | Advanced Encryption System to Improvise the System Computing Speed: The main objective of this project is to improve the security of data transmission as well as to enhance the computing speed by implementing AES algorithm based on FPGA. This mathematical design and simulation are carried though the VHDL code. |

14 | AMBA-Advanced High Performance Bus IP Block: The main goal of this project is to design an Advanced Microcontroller Bus Architecture using Advanced High Performance Bus (AHB). This is modeled and simulated by using VHDL code by implementing master and slave blocks. |

15 | A Multichannel Multimode RF Transceiver with DSM: This project aims to design RF multichannel and multimode transmitter and receiver architecture using Delta Sigma modulator. In this project, VHDL programming language is used for implementing these two architectures. |

16 | Asynchronous Transfer Mode Knockout Switch Concentrator: In this project, concentrator of Asynchronous Transfer Knockout switch is designed and modeled using VHDL and VIS tool. This switch is used in virtual circuit packet networks and datagram applications. |

17 | Behavioral Synthesis of Asynchronous Circuits: This project presents behavioral synthesis method of for asynchronous circuits. The balsa implementation and asynchronous implementation template are the key elements in this design. |

18 | Building an AMBA AHB Compliant Memory Controller: The main aim of this project is to build a memory controller (MC) based on Advanced Microcontroller Bus Architecture (AMBA) for controlling the system memory with main memory consisting of ROM and SRAM. |

19 | Implementation of Carry Tree Adder: VLSI designs of carry-tree adders (or parallel-prefix adders) are known as the best performance adders compared with normal binary adders. This project implements these adders like kogge-stone, spanning tree and sparse kogge-stone adders. |

20 | Fixed Angle of Rotation Using CORDIC Designs: The main objective of this project is to rotate vectors through fixed and known angles which are the necessary requirement in robotics, games, image processing, etc. In this, vector rotation through specific angles is achieved by coordinate rotation digital computer (CORDIC) design. |

21 | Design of FPGA based 32-bit Floating Point Arithmetic Unit : This project is intended to prepare VHDL code for implementing FPGA based floating point arithmetic unit. This VHDL code is further simulated in MATLAB for checking the results. |

22 | Design and Synthesis of a Field Programmable CRC Circuit Architecture: This project illustrates the design and development of FPGA based Cyclic Redundancy Check (CRC) computation circuit. This uses matrix based computation technique for deriving the array of processing cells. |

23 | Design of an On-Chip Permutation Network for Multiprocessor SOC: This proposed project implements an on-chip design which supports for traffic permutation in the multiprocessor system on-chip applications. This design can be used for real time applications as high-performance inter-processor communication. |

24 | VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design: This project is intended to design a watermarking chip that can be inserted into digital camera for watermarking the images. This project deals with two such VLSI architectures for implementing visible watermarking schemes. |

25 | Design and Implementation of Efficient Systolic Array Architecture: The objective of this project is to develop a hardware model of systolic array multiplier which can be used to perform binary multiplication using VHDL platform. This design is implemented on FPGA and simulated in Isim software. |

26 | VHDL Environment for Floating Point Arithmetic Logic Unit : This project aims to design and simulate the pipeline approach based floating point ALU using VHDL. This pipelining approach allows the multiple instructions to execute simultaneously. |

27 | Design and Implementation of High Speed DDR SDRAM Controller: This project implements a burst data transfer based high speed DDR SDRAM controller that synchronizes the transfer of data between DDR SDRAM and the rest of embedded system circuitry. This code is developed by using VHDL. |

28 | Design and Synthesis of QPSK: In this project, one of the popular modulation technique used in satellite radio applications i.e., QPSK modulation is implemented by using reversible logic gates. This modulation technique is modeled using VHDL code. |

29 | Design of Multi Value Logic Using Quantum Dot Gate FET: This project aims to increase the bit handling capacity of logic circuits by designing a circuit model of three-stage quantum dot gate field effect transistors (QDGFETs). This three stage design is implemented for different combinational circuits like comparator and decoder. |

30 | Design and Simulation of FFT Processor Using Radix-4 Algorithm Using FPGA: This project simulates and synthesizes the 256-point Fast Fourier Transform (FFT) processor with Radix-4 algorithm which is popularly used in WLAN and Orthogonal Frequency Division Multiplexer (OFDM). This project is designed by using VHDL coding. |

31 | Design and Implementation of 32 bit RISC Processor: The main objective of this paper is to implement a 32 bit Reduced Instruction Set Computer (RISC) using XILINK VIRTEX4 tool. In this design 16 set instructions are designed where each instruction is executed in one clock cycle with 5 stage pipelining technique. |

32 | VHDL Model of Smart Sensor: The aim of this project is to build a VHDL model of smart sensor by implementing algorithm for smart sensor with noise cancellation using IEEE 1451 communication standard. The complete simulation of this project is carried by VHDL program. |

33 | Fuzzy based PID Controller using VHDL for Transportation Application: This project implements the PID controller for cruise system in order to avoid the collision between the vehicles. This PID controller is implemented based on Fuzzy algorithm which is simulated using VHDL language. |

34 | Implementation of Bus Bridge between AHB and OCP: The basic idea of this project is to design a bus bridge between common and standard protocols namely Advanced High performance Bus (AHB) and Open Core Protocol (OCP) which are popular communication protocols used in System On-chip applications. |

35 | Design of Control Area Network Protocol: This project aims to design a Controlled Area Network (CAN) protocol using Verilog HDL code by using Eight to- Eleven modulation technique in place of conventional Software Bit Stuffing (SBS) technique. |

36 | DMA Controller for AMBA Bus IP Core: This project gives the complete development process of DMA controller for an on-board computer using VHDL code. This FPGA based DMA controller can be useful for satellite on-board computers. |

37 | High Precision Stepper Motor Controller Implementation on FPGA: The aim of this project is to design FPGA based stepper motor controller using VHDL code. The control function of the stepper is achieved by implementing Pulse Width Modulation technique. |

38 | Design and Modeling of I2C Bus Controller: The objective of this project is to design and model the I2C bus protocol by using VHDL code to present the I2C protocol working between master-slave communication via I2C bus so that real time implementation results can be compared with simulated results. |

39 | Design and Implementation of CPLD based Solar Power Saving System: This project is intended to utilize the solar energy in efficient manner by implementing Complex Programmable Logic Device (CPLD) for street lights and automatic traffic controllers. This design logic is implemented by VHDL code. |

40 | Designing Fuzzy Based Mobile Robot Controller using VHDL: This project demonstrates the design of fuzzy logic based algorithm for navigating or controlling the autonomous mobile robot. This algorithm is first simulated in MATLAB and then translated into VHDL for hardware implementation. |

41 | Design and Implementation of a Real-time Traffic Light Control System: In this project, a real-time traffic light control system algorithm is designed on FPGA using VHDL code. The VHDL code is first modeled and simulated and then downloaded to FPGA board to verify its functioning. |

42 | FPGA Based Digital Space Vector PWM Three Phase Voltage Source Inverter: The main idea of this project is to design FPGA based DSVPWM controller for three phase voltage source inverter to achieve high performance and low power motor drive. This inverter design is carried by using VHDL code. |

43 | Performance Evaluation of Complex Multiplier Using Advance Algorithm: This project aims to use ancient Vedic mathematics to perform complex multiplier operation by VHDL implementation. The simulation results of conventional booth algorithm and Vedic sutra for 4 bit multiplication are illustrated in this project. |

44 | A Highly linear CMOS Gm-C Low Pass Filter for Mobile Communication: In this project, a highly linear and wide tunable Operational Transconductance Amplfier (OTA) based Butterworth filter is designed for direct conversion receiver. This design is simulated using CMOS 90nm technology. |

45 | Design of High Throughput DCT Core Design by Efficient Computation Mechanism : The main objective of this project is to design VLSI hardware of the Discrete Cosine Transform algorithm for image compression applications. The FPGA implementation is used for the design of DCT using VHDL code. |

46 | Low Power QVCO using Adiabatic Logic: This project reduces the power consumption in VLSI design of Quadrature Voltage-Controlled Oscillator (QVCO) by implementing adiabatic logic technique. This design is simulated in standard 0.18 RF-CMOS machinery. |

47 | Low Power Adaptive Viterbi Decoder Design for Trellis Coded Modulation: In this project, a low power adaptive viterbi decoder algorithm is implemented to overcome data corruption in data communication channels especially in case of trellis coded modulation systems. This FPGA based decoder is simulated in Xilink software. |

48 | VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression: This project is proposed to design an efficient discrete wavelet transform algorithm for image compression. This algorithm is first modeled and simulated in MATLAB and then implemented on VHDL platform. |

49 | Implementation of OFDM System using IFFT and FFT: The main aim of this project is to design Orthogonal Frequency Division Multiplexing (OFDM) system using core signals processing blocks like IFFT and FFT using VHDL code. These blocks are simulated on Xilink software. |

50 | Design and Implementation of Hamming Code on FPGA using Verilog: This project demonstrates the design and hardware implementation of FPGA based hamming encoder and decoder systems for wireless transceiver systems. This FPGA based system is implemented using VHDL code while Xilink is used for hardware implementation. |

51 | Gabor Filter for Fingerprint Recognition using Verilog HDL: The main focus of this project is to simulate the Gabor filter for the enhancement of fingerprint images so that extraction of minutia is done using VHDL code. In this, Gray-scale filtering is used in Gabor filter deign. |

52 | Floating Point Fused Add-Subtract and Fused Dot-Product Units: This project aims to perform simultaneous floating point multiplication and add-subtract operations by implementing Floating Point Fused Add-Subtract and Fused Dot-Product Units in parallel. These units are simulated using Xilink software. |

53 | Improvement of the Orthogonal Code Convolution Capabilities using FPGA Implementation: In this project, FPGA based Orthogonal Code Convolution is implemented for data communication systems using VHDL code. This project also presents the error detection improvement for 8-bit and 16 bit orthogonal code. |

54 | Design of Non-Volatile Memory Based On Improved Writing Circuit STT-MRAM Technique: This project proposes the design of Spin transfer torque and Magnetic flip-flop based STT-MRAM with CMOS technology in order to reduce the power and area as compared with SRAM or SRAM. |

55 | Address Remapping in Arithmetic Functions using ROM Based Approximation Approaches: The main aim of this project is to increase the function evaluation to order to make ROM fast enough for accessing. This is achieved with non-uniform segmentation and for reducing the size, ROM address remapping is used. For synthesizing this design VHDL is used. |

56 | Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology: This project gives a complete design of high speed and low-power of flip flops like DET, SET, C2CMOS and TSPC flip flops having less number of transistors. These can be used in various applications including buffers, microprocessors, digital VLSI clocking system, registers, etc. |

57 | Low Power H.264 Video Compression Architecture for Mobile Communication: This project is designed to reduce the memory access and computational cost for Variable Block Size for Motion Estimation (VBSME) using pixel truncation without degrading picture quality. This VLSI architecture saves 53 % of energy as compared with conventional full-search architecture. |

58 | Enhanced Scan in Low Power Scan Testing: In this project, peak test power and capture power can be reduced by implementing two routing driven architectures which only activate subset of scan flip flops for capturing test responses or shifting of test data. |

59 | Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure: This project implements the power gating technique to mitigate the noise with body tied structure in triple well. In this test chip is fabricated in 65nm process. |

60 | VHDL Implementation of Universal Asynchronous Receiver Transmitter: The main objective of this project is to implement Universal Asynchronous Receiver Transmitter (UART) using VHDL code. This design facilitates the auto tuning baud generation and also includes the various error detections like stop error, parity error, break error and overflow error. |

61 | Design and ASIC Implementation of a 3GPP LTE Advance Turbo Encoder and Turbo Decoder: This project aims to design an efficient VLSI architecture for 3GPP advanced turbo decoder by using convolution interleaver. This turbo decoder is coded by VHDL code and simulated in modelsim. |

62 | Design of Low Power Multiplier using Compound Constant Delay Logic Style: This project compares the different multipliers like Wallace tree multiplier; array multiplier and Baugh wooley multiplier using compound constant delay logic with static and dynamic logic styles. The synthesis of this design is carried by VHDL and these are simulated in Xilinx tool. |

63 | Design of Flash ADC using Improved Comparator Scheme: This project presents the 4 bit flash analog to digital converter consisting of comparators and MUX based decoder by eliminating the use of ladder resistor network. It can be fully implemented on CMOS technology. |

64 | High Performance Flash Storage System Based on Virtual Memory and Write Buffer: This project improves the performance of flash memory based systems by cooperative virtual memory and writes buffer management. This work is carried on VLSI platform in the form of VHDL using Xilinx tool. |

65 | An Effective Leading Zero Anticipation for High Speed Floating Point Addition and Subtraction: In this project, a high speed floating point addition and subtraction is implemented by proposing an effective Leading Zero Anticipation (LZA) logic using verilog HDL. This design can be useful CISC, RISC, DSP and microprocessor applications. |

66 | FPGA Implementation of an LFSR based Pseudorandom Pattern Generator for MEMS Testing: This project presents the implementation of Linear Feedback Shift Register (LFSR) based pseudorandom pattern generator using VHDL on FPGA platform. This is designed by using mixed mode modeling technique in a modular manner. |

67 | Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST Implemented in HDL: This project deals with the implementation of Linear Feedback Shift Register (LFSR) with bit-swapping to optimize the power. This design can reduce the total power consumed about 50 % than that of conventional LFSR. |

68 | Design and Implementation of Vending Machine using Verilog HDL: This project deals with the implementation of FPGA based vending machine which uses less power and gives fast response as compared with microcontroller based vending machine. The algorithm for this machine is implemented by using VHDL, simulated in Xilink simulator and implemented in FPGA development board. |

69 | High-Speed Low-Complexity Reed-Solomon Decoder: This project demonstrates the low complexity and high speed Reed-Solomon decoder using Pipelined Berlekamp-Massey Algorithm and its folded architecture with CMOS technology. This RS decoder is modeled and simulated in verilog HDL to verify its functionality. |

70 | FM Radio Receiver with Digital Demodulation: In this project, a simple demodulator circuit is designed using phase lock loop method on FPGA. This demodulating of FM signals is carried out using VHDL code. |

71 | Implementation of High-Speed Pipeline VLSI Architectures: The main objective of this project is to design high speed and efficient pipeline architectures for the computations of 2D and 1D discrete wavelet transform by minimizing number of clock cycles and operating frequency for performing DWT computations. |

72 | Design of Phase Frequency Detector and Charge Pump for High Frequency PLL: This project implements the new phase frequency detector and charge pump using cadence 0.18 micrometer CMOS process. This can be used for low power and high speed applications such as low jitter applications. |

73 | Design of Cache Memory with Cache Controller Using VHDL: The main aim of this project is to design FPGA based cache memory for detecting the cache miss and also to implement a cache controller for tracking the cache miss in cache memory. This design is performed by mixed style of modeling in VHDL. |

74 | An On Chip Design for Prepaid Electricity Billing System: The purpose of this circuit design is to implement an advanced and highly reliable prepaid electronic energy meter using VLSI technology. This VLSI design is implemented by ASIC design by modeling and simulating in this project. |

75 | High Speed Network Devices Using SRL16 Reconfigurable Content Addressable Memory (RCAM): In this project, SRL16 Content Addressable Memory (CAM) unit is designed by using VHDL and FPGA technique. Compared with the traditional CAM design methods, this design gives better results in terms of parallel and fast search capabilities. |

76 | IP-SRAM Architecture at Deep Submicron CMOS Technology : This project reduces the power dissipation in VLSI circuits by designing new SRAM architecture with IP-SRAM technique. This architecture is designed using 180nm technology. |

77 | Glitch free NAND based Digitally Controlled Delay Line for Spread Spectrum Clock Generator: The objective of this project is to avoid the glitch problem in conventional NAND based digital control delay lines (DLDL). This project deals with the implementation of glitch free NAND based DCDL on SSGC (Spread Spectrum Clock Generator). |

78 | Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment : This project aims to design, simulate, test and implement different bit Carry Look Ahead (CLA) adder based on VHDL and to compare their results. In this 4, 8 and 16-bit CLA adders are implemented using VHDL and simulated using Modelsim software. |

79 | High speed VLSI implementation of 256-bit Parallel Prefix Adders: This project present the new approach for the redesign of parallel prefix adders with 128 width operands of different parallel adders on Xilink Sprtan FPGA. This VLSI based design gives better performance than that of conventional adders. |

80 | FPGA Implementation of Mutual Authentication Protocol using Modular Arithmetic: This project aims to design hardware efficient protocol for RFID system by implementing tag-reader mutual authentication scheme which is more secure for external attacks and also consumes less logic elements. This is designed by VHDL and simulated in Xilink simulator. |

81 | Design of Data Link Layer using Wi-Fi MAC Protocols: The main aim of this project is to design the MAC layer of IEEE 802.11 standard which is mainly used for Wi-Fi communication products. This Wi-Fi transmitter is designed and simulated using VHDL and simulator respectively. |

82 | Implementation of Overlap based Logic cell and Its Power Analysis: This project improves the static power consumption in CMOS technology by clock overlap-based logic. This project implements a new architecture of dynamic/static edge triggered flip-flops with the overlap logic. |

83 | Low Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN: This project demonstrates the two adder compressor architectures which are used to implement multipliers and FFTs. This project deals with the combined implementation of these two adders at logic, electrical and physical levels. |

84 | FPGA Implementation of UTMI and Protocol Layer for USB 2.0: This projects implements the USB 2.0 Macrocell Transceiver Interface (UTMI) and protocol layer of USB core on FPGA by using VHDL code and Xilink software. This design can perform error detection, data encoding and decoding operations in an efficient way. |

85 | Review of 5 stage Pipelined Architecture of 8-Bit Pico Processor: This project demonstrates the increased performance of 8-bit Pico processor by implementing pipelining technique. This 8-bit Pico processor is used for small embedded applications and also used for educational purpose. |

86 | Design of On-Chip Bus OCP Protocol with Bus Functionalities: This project implements the Open Core Protocol (OCP) using VHDL for providing the lossless communication. This design provides bus functionalities like burst transactions, simple transactions, out-of-order transactions and pipelined transactions. |

87 | FPGA Implementation of Controller Design for Remote Sensing Systems: In this project, a controller is designed for remote monitoring and remote sensing system that can be communicated through GSM network. This design is performed by VHDL and implemented on FPGA hardware. |

88 | Test Pattern Generation Using BIST Schemes: This project generates the different test patterns using Built-In Set-Test schemes by a class of MISC (Multiple Single Input Change) sequences. This design is carried by VHDL and test patterns are simulated in Modelsim. |

89 | A Design Technique for Faster Dadda Multiplier: The main aim of this project is to achieve the faster multiplication by combining two design techniques; partitioning of the partial products and adding them using hybrid adder. Based on this design, 8, 16, 32 and 64-bit Dadda multipliers are implemented. |

90 | An Efficient Retouched Bloom Filter Based Word-Matching Stage Of BLASTN: This project implements the new algorithm for Retouched Boom Filter for genomic sequence database scanning based on FPGA architecture. This architecture accelerates the word matching stage of BLASTN which is a bio-sequence search tool. |

91 | VLSI Implementation of Single Cycle Access Structure for Logic Test in FPGA Technology: This project implements an FPGA based new test structure for single cycle access test by proposing priority encoder in the structure to speed up the execution process. This design is developed using VHDL code, simulated in Modelsim and synthesized in Xilink software. |

92 | Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR: This project aims to generate weighted patters without changing the structure of adder by Ex-Oring counter and gray code generator with seed generated by the low power linear feedback shift register (LP-LSFR). |

93 | Sleepy Stack Approach Based Low Power Flip Flop: The objective of this project is to design and implement the low power flip-flops using a new VLSI structure of sleepy stack approach for reducing the leakage power consumption. |

94 | Low Power High Performance Double Tail Comparator: This project presents a new structure of double tail comparator with additional circuitry in order to achieve high performance, reduction of delay and low power. This hardware design is implemented on FPGA board using VHDL coding. |

95 | Design of a Low Drop-Out Voltage Regulator using VLSI: This project enhances the performance of Low Drop-Out (LDO) voltage regulator that can operate with low input-output differential voltage 45nm CMOS technology. This CMOS layout for the LDO is achieved by VLSI. |

96 | VLSI Architecture of Arithmetic Coder Used in SPIHT : This project improves the throughput of Arithmetic Coding technique in SPIHT (set partitioning in hierarchical trees) image compression by using high speed architecture based on FPGA. |

97 | FPGA Based ECG Signal Noise Suppression: This project aims to suppress the noise in ECG signals by using two median filters with size of 91 sample points and 7 sample points respectively. This is achieved by implementing FPGA based design using VHDL. |

98 | Low Power and High Speed Conditional Push-Pull Pulsed Latches: This project goal is to implement a high performance and energy efficient pulsed latches for VLSI systems based on the new topology. This topology depends on a push-pull final stage driven by two split paths with a conditional pulse generator. |

99 | An Enhanced Low Cost High Performance Image Scaling Processor Using VLSI: In this project, a high performance and less memory required algorithm is implemented for VLSI based image scaling processor. This design includes filter combining, reconfigurable dynamic techniques and sharing of hardware to reduce the cost. |

100 | Design of Finite Impulse Response Filter Using Distributed Arithmetic of Lookup Table: This project improves the performance of FIR filter by designing it with distributed arithmetic of three dimensional lookup table instead of multiplier. This design is implemented in Xilinx software and FPGA. |

101 | Pipelined Radix-2k Feedforward FFT Architectures: This project presents the Radix-2K feedforward FFT architectures which can be used for any number of parallel paths or samples which is power of two. These are hardware efficient and very attractive of FFT computations. |

102 | Performance Analysis of High Efficiency Low Density Parity-Check Code Decoder for Low Power Applications: This project implements high efficient and Low Density Parity-check Code (LDPC) Decoder architecture design of error detection and correction applications. This LDPC architecture is synthesized on Xilinx and simulated using Modelsim. |

p. jyothi says

i want to know about a moduler shared l2memory design for 3d integration?